To increase efficiency and flexibility of digital computers, computer systems have been developed using multi-processor configurations which can process a number of programs concurrently. Further increase in efficiency has been achieved by using direct access controllers to permit direct communication between peripheral devices. Many of the prior art systems are not fully modular and thus require substantial system redesign to upgrade a smaller system to a larger system. Due to lack of redundancy they will also suffer a complete system failure if any vital sector fails. Some modular systems have been developed which allow both flexibility of growth and redundancy. However, they require that each direct access controller or processor (hereinafter referred to generically as a controller) is capable of performing all operations so that if all but one controller fails, the system would remain functional. This technique requires bus switching to permit sharing of peripheral devices such as memory and external I/O. Such sharing of devices on a common bus, however, would mean that two or more controllers might attempt to simultaneously access the shared bus thereby requiring one or more controllers to wait. When this contention occurs an arbiter device must determine which controller shall be granted access to the shared bus and which shall be denied access. It is often desirable that this arbiter device not allow any controller to be permanently locked out of the bus and that it permit only one controller to access the bus at any one time. Thus a dynamically prioritized bus access arbiter is needed to rotate access among requesting controllers.
It is also desirable that the arbiter be capable of dual mode operation so that it can operate in both a cycle shared mode and a lock out mode. In the cycle shared mode which is desirable for access to a common memory bus, access is given for only one cycle at a time. Therefore, all controllers can access memory even if a failure in the system would cause a permanent request for memory from one controller. If the lock out mode is used, desirable for access to external peripheral devices such as printers, the arbiter will maintain uninterrupted access to a controller as long as the access request signal is maintained. This will result in a lock out of all other controllers, however a failure of one controller, resulting in a permanent request for access would permanently lock out all others. The elimination of the permanent lock out problem requires the addition of watchdog circuitry which monitors normal program flow and resets the system when a failure is detected.
Known arbiter devices are relatively complex often consisting of another processor. This complexity makes it difficult to use them in a distributed network. As an example, a distributed arbiter could be made up of one arbiter circuit used in the cycle shared mode to control access to the memory bus and another arbiter circuit operated in the lock out mode to control access to the I/O bus. Thus failure of the arbiter in one sector will not necessarily lead to a complete system failure. In addition, known arbiter circuits do not permit a cycle shared mode of operation.